The present application relates to integrated circuits, modules, and packaging and connection methods for them; and more particularly to multi-chip modules, and to optional use of a single integrated circuit in either a standalone package or a multi-chip module.
Previous solutions for a controller to support both two-adjacent-sided SIP bonding and a low cost discrete package (such as four-sided QFP) would involve choosing a larger QFP with pin-count=2×(pad count), where only two sides are bonded, and pins on sides 3 and 4 are wasted and not used. In addition to increased package cost, the larger package may violate mechanical size requirements.
An alternative package, a BGA (Ball-Grid-Array) achieves support for both the SIP configuration and discrete controller packaging and allows (pin-count)=(pad-count) with pads only on two-sides, and satisfies the mechanical size requirements. However, the BGA package requires an internal substrate/RDL that makes it significantly more expensive than the four-sided QFP mentioned above.
Mechanical and Cost Factors in Die Packaging
Chip die packaging is commonly selected to minimize cost and/or mechanical footprint. The ultimate minimal limit of one of these two usually comes at the expense of the other. The smallest mechanical package for a given die is usually the most expensive packaging technology, and the least expensive packaging substrate/RDL technology for a given die-size typically does not offer the minimum mechanical footprint.
Two common package types can illustrate this for a given design, the BGA (ball grid array) and the QFP (quad flat pack). For an 80 pad design, a BGA device footprint is 9 rows of 9 balls. For the equivalent design in a QFP, the device footprint would be four sides at 20 pins per side. In prior art available packaging technology, with equivalent surface-mount manufacturing tolerances, the BGA can achieve a smaller device footprint for the same 80 pads needed. However, the BGA is a more costly solution which employs, in addition to bond wires, an internal substrate to re-route the die's two or four sides of in-line pads to a closely packed 9×9 array of balls. This embedded substrate adds significant cost to the BGA package assembly, while a QFP largely consists of only an inexpensive lead frame and bond wires. In high volume consumer-level products, this package cost difference can significantly impact product margin, and subsequently, the financial success of the product.
QFP packaging needs fairly homogeneous pinout densities if it is to maximize cost-effectiveness. For example, if 80 pins must be brought out, a QFP80 is much cheaper than a QFP160; however, use of a QFP80 requires that exactly 20 pins per side must be used. Thus if the system configuration dictates that 30 pins must be used on one particular side, a QFP80 cannot be used.
Mechanical Assembly: Discrete Memory+Controller Packaging Vs. SIP
There are two main approaches to die/product packaging for industry-standard Host-based Nonvolatile electronic storage devices (Flash storage cards or Flash drives):                1. Discrete—Memory and Controller are packaged discretely and are then soldered to a PC board/substrate along with interface connector (e.g. USB) and needed support circuitry (resistors, capacitors, inductors, etc.).        2. SIP (System-in-package)—Memory and Controller dies stacked on a substrate with card edge connector—with only bond wire interconnects, and limited support circuitry (resistors, capacitors, inductors, etc.)—Assembly is then molded in plastic.Pad-Limited Vs. Core-Limited        
Another major factor in package selection is whether the design is pad-limited or core-limited. In a pad-limited design, the minimum die-size possible is dictated by the arrangement of pads around a smaller logic core—more logic could fit without growing the die-size. In a core-limited design, the minimum die size possible is dominated by the logic core dimensions—extra pads could fit without growing the die-size.
The most efficient/cost-effective of these two is core-limited. Pad-limited designs are considered to “waste” silicon with un-used/blank logic area. The final die area (length and width) of pad-limited design is dictated by the (number of pads)×(pad width) for the two dimensional edges of the design.
Similarly, since pads have a set depth dimension (measured from edge of die to edge of internal core), a core-limited design could potentially waste perimeter die area (pad ring) if the pads are placed on three or four sides, when they might have all fit on just one or two sides. The final die area (length and width) of a core-limited design is dictated by the two dimensional edges of the core logic+(# of sides of die that require pads)×(pad depth)×(length of that side of die). An exception to this is the use of a physical design method of circuit under pad (CUP) that allows the pad ring to overlay the perimeter of the logic area rather than abut it. CUP is a relatively new method, and requires several other design considerations that limit its broad applicability.
Ultimately, these pad arrangements (pad packing, pad reduction, and pad placement methods) and packaging technology decisions will impact the overall die-size and cost of the design. Knowing this, certain mechanical and electrical approaches and methods can be exploited to minimize overall system cost in a potentially die-size neutral way.
Two-Sided vs. Four-Sided
Typically, a chip design team would select either a two-sided OR a four-sided pad arrangement for a die that would require a bonded package. If both were needed, two separate die may be designed where each one used the optimal pad selection and arrangement to minimize die and package cost. Alternatively, the minimum number of pads to accommodate both packages could be used, but a costly RDL would be needed to minimally distribute the two sides of pads to a four-sided package, due to the length limitation on bond wires.
Two-sided (L-shaped) die bonding is the preferred arrangement for a memory controller die that is to be assembled in a SIP packaging scheme where it is stacked atop a larger memory die (that dictates the maximum package size) and connected with bond wires to common pads on the memory die via a shared substrate. When the controller is much smaller than the memory device, only pads on two sides of the controller can effectively reach the shared substrate through mechanical-length-limited bond wires.
Four-sided (full square or rectangle) die bonding is the preferred arrangement for low-cost QFP packaging when just the controller is assembled in a single package (no memory or substrate stacking). When lowest cost and smallest mechanical footprint are key design goals, the minimum number of pins per side in a QFP can offer the optimal configuration. Typically, the total number of required pads are near equally distributed across the four sides (Ex: ˜80 total pads→20 pads per side of four-sides).
The two-sided arrangement is fundamentally at odds with the four-sided arrangement, since the same 80 pads noted above would typically need to be split up to ˜40 per side of two sides (L-shaped). Without further handling, this 40-per side L-shape (with no pads on sides 3 and 4) would then require a 160-pin QFP if it were to simultaneously support both two-sided and four-sided package bonding (2 sides, 80 pins, would be unused/wasted in the QFP). Either this higher pin-count (only two sides bonded) QFP package costs more than a lower pin-count (four-sides bonded) QFP, or it is mechanically larger than a (four-sides bonded) QFP, or both. The 40 per side QFP would thus add unnecessary cost, or possibly exceed the mechanical form factor, or both.
If such a dual-purpose (dual package-bonding-capable—both SIP and QFP) die were needed (e.g. to cost-effectively support a plurality of on-board data interfaces that serve multiple package and product configurations), then certain considerations would need to be addressed to provide optimal pad, power, and functional configurations where both cost and mechanical package size were minimized simultaneously for the multiple configurations.